1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including FINFETs.
2. Description of the Related Art
Because a semiconductor memory device is becoming widely used as a memory device for a portable terminal device, for example, a cellular phone, a PDA, a digital camera, etc., the demand for miniaturization of the semiconductor memory device is increased. To this end, a semiconductor memory device should be designed to reduce a layout area size of a core region of the semiconductor device so more circuit elements can be arranged on the semiconductor device and/or the overall size of the semiconductor device may be reduced.
FIG. 1 is a circuit diagram illustrating a core region of a conventional semiconductor memory device.
Referring to FIG. 1, a core region of a conventional semiconductor device may include a memory cell array 1, a precharge circuit 21, a bit line sense amplifier 22 and a data I/O circuit 23. The memory cell array 1 may read and/or write data in response to a signal transmitted via a word line WL and a bit line pair BL and /BL. The precharge circuit 21 may precharge the bit line pair BL and /BL to a precharge voltage level in response to a precharge control signal PEQ. The bit line sense amplifier 22 may detect and/or amplify a voltage difference of the bit line pair BL and /BL in response to a sensing control signal pair LA and /LA, and the data I/O circuit 23 may transmit data of the bit line pair BL and /BL to a local data I/O line pair LIO and /LIO or may transmit data of the local data I/O line pair LIO and /LIO to the bit line pair BL and /BL in response to a column selecting signal CSL.
The components of FIG. 1 are explained below.
The memory cell array 1 may include a plurality of memory cells MC, each of which includes at least one n-type Metal Oxide Semiconductor Field Effect Transistor (n-MOSFET) (not shown) or p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) (not shown) and a capacitor (not shown) which may be connected between the word line WL and the bit line pair BL and /BL.
The precharge circuit 21 may include first and second n-MOSFETs NM1 and NM2, which may be connected directly between the bit line pair BL and /BL, may have a gate to which a precharge control signal PEQ may be applied, and may precharge the bit line pair BL and /BL to a precharge voltage VCC/2 level in response to the precharge control signal PEQ. The precharge circuit 21 may also include a third n-MOSFET NM3, which may be connected between the bit line pair BL and /BL, may have a gate to which the precharge control signal PEQ may be applied, and may precharge the bit line pair BL and /BL to the precharge voltage VCC/2 level in response to the precharge control signal PEQ.
The bit line sense amplifier 22 may include a p-type sense amplifier and an n-type sense amplifier that may be connected to the bit line pair BL and /BL, respectively. The p-type sense amplifier may be serially connected between the bit line pair BL and /BL; may include first and second p-MOSFETs PM1 and PM2, which may have a gate connected to the bit line pair BL and /BL and a common source to which a sensing control signal LA may be applied; and may detect data of a low level of one of the bit line pair BL and /BL to amplify the other line of the bit line pair BL and /BL to a power voltage VCC level. The n-type sense amplifier may be serially connected between the bit line pair BL and /BL; may include fourth and fifth n-MOSFETs NM4 and NM5, which may have a gate connected to the bit line pair BL and/or /BL and a common source to which an inverted sensing control signal /LA may be applied; and may detect data of a high level of one of the bit line pair BL and /BL to amplify the other line of the bit line pair BL and /BL to a ground voltage level, for example, 0 Volts.
The data I/O circuit 23 may include a sixth n-MOSFET NM6, which may be connected between the bit line BL and the local data I/O line LIO and may have a gate to which the column selecting signal CSL may be applied, and a seventh n-MOSFET NM7, which may be connected between an inverted bit line /BL and an inverted local data I/O line /LIO and may have a gate to which the column selecting signal may be applied; and may electrically connect the bit line pair BL and /BL and the local data I/O line pair LIO in response to the column selecting signal CSL.
An operation of the conventional semiconductor memory device of FIG. 1 is explained below with reference to FIG. 2.
For illustrative purposes, assume that data having a value of “0” is stored in a 0-th memory cell MC0 of the memory cell array 1 and the conventional semiconductor memory device in FIG. 1 reads data in the 0-th memory cell MC0 by a reading operation.
At a time T0 in FIG. 2, the conventional semiconductor memory device may be in a precharge state, word lines WL0 to WLN may have a low level, and a bit line precharge control signal PEQ may have a high level. The n-MOSFETs NM1 to NM3 of the precharge circuit 21 may be activated to precharge the bit line pair BL and /BL to a precharge voltage VCC/2.
At a time T1, the bit line precharge control signal PEQ may transition from a high level to a low level and the 0-th word line WL0 may transition from a low level to a high level so that the 0-th memory cell MC0 may be selected and data of the 0-th memory cell MC0 may be outputted to the bit line pair BL and /BL. As a result, a voltage of the bit line BL may gradually drop and the inverted bit line /BL may maintain the precharge voltage VCC/2 level.
At a time T2, a voltage of a sensing control signal LA may change from the precharge voltage VCC/2 to a power voltage VCC and a voltage of an inverted sensing control signal /LA may change from the precharge voltage VCC/2 to a ground voltage, for example, 0 Volts so that the power voltage VCC may be applied to the sources of the first and second p-MOSFETs PM1 and PM2 of the bit line sense amplifier 22, and the ground voltage, for example, 0 Volts may be applied to drains of the fourth and fifth n-MOSFETs NM4 and NM5.
At a time T3, if a voltage difference between the sensing control signal LA and the bit line BL is greater than a threshold voltage VTm of the MOSFET, the second p-MOSFET PM2 of the bit line sense amplifier 22 may be activated to apply the power voltage VCC to the inverted bit line /BL so that a voltage of the inverted bit line /BL may be increased. If a voltage difference between the inverted sensing control signal /LA and the inverted bit line /BL is greater than the threshold voltage VTm of the MOSFET, the fourth n-MOSFET NM4 may be activated to drop a voltage of the bit line to the ground voltage, for example, 0 Volts.
Accordingly, if the voltage difference between the sensing control signal LA and the bit line BL or the voltage difference between the inverted sensing control signal /LA and the inverted bit line /BL is greater than the threshold voltage VTm of the MOSFET, the bit line sense amplifier 22 may be activated and start an operation for amplifying the bit line pair BL and /BL.
At a time T4, if an amplification operation of the bit line pair BL is stabilized, the column selecting signal CSL may transition from a low level to a high level and data of the bit line pair BL may be transmitted to the local data I/O line pair LIO and /LIO so that data of the memory cell MC0 may be read.
At a time T5, if the read operation is completed, the 0-th word line WL0 may transition from a high level to a low level again to keep data of the 0-th memory cell MC0 in a storing state.
At a time T6, for the next read or write operation, the bit line precharge control signal PEQ may transition from a low level to a high level again to precharge the bit line pair BL and /BL to the precharge voltage VCC/2, whereby the semiconductor memory device becomes the precharge state again.
A write operation of the semiconductor memory device is performed based on the same principles as described with respect to the read operation described in FIG. 2, and thus, a description of the write operation will be omitted for the sake of brevity.
As described above, in a conventional semiconductor memory device, a MOSFET is used to form the memory cell MC, the precharge circuit 21, the bit line sense amplifier 22, and/or the data I/O circuit 23 and may be activated or deactivated to read or write data of the memory cell in response to a plurality of control signals PEQ, LA, /LA, and CSL and a voltage level of the bit line pair BL and /BL.
The MOSFET of FIG. 1 is a planar type transistor, and when the MOSFET is an n-MOSFET, as shown in FIG. 3, the MOSFET includes an n-type drain and an n-type source formed to be separated from each other and a gate electrode formed on a p-type substrate between the n-type drain and the n-type source.
The n-MOSFET may apply a voltage of more than the threshold voltage VTm to a gate to sufficiently induce electrons on a surface of the gate to form a channel so that an electric current may flow between the source and the drain through a channel. The conventional n-MOSFET has the threshold voltage VTm of about 0.7 Volts.
Even though not shown, similar to the n-MOSFET of FIG. 3, the p-MOSFET includes a p-type drain and a p-type source formed to be separated from each other and a gate electrode formed on an n-type substrate between the p-type drain and the p-type source and has the threshold voltage VTm of about 0.7 Volts.
Moreover, the second p-MOSFET PM2 of the bit line sense amplifier 22 may be activated to start the sensing operation if a voltage difference between the sensing control signal LA and the bit line BL is greater than about 0.7 Volts and the voltage difference VGS between the gate and the source of the second p-MOSFET PM2 is greater than about 0.7 Volts as shown at the time T3 of FIG. 2.
As described above, in a conventional semiconductor memory device the transistors are horizontally formed on the substrate as shown in FIG. 3 and occupy a relatively wide area and thus, the transistors cannot be formed in a smaller area without detrimental affects.
For example, conventionally, if an area on which the transistor is formed is reduced to reduce the size of the semiconductor memory device; the length of the gate of the MOSFET is reduced, which may cause several problems. For example, the source and the drain of the MOSFET may be too closed to each other. In this case, the impurity doping density should be increased, and the channel area is affected by interaction between the source and the drain. As a result, a characteristic of the transistor as an active switching element, which controls an operation of the transistor by adjusting a gate voltage of the MOSFET, may be degraded so that electrical characteristics of the MOSFET, for example, a stable threshold voltage, may be degraded.
As described above, there are limitations to reducing the layout area size of a core region of the conventional semiconductor memory device, and even though the layout area size of the core region may be reduced by reducing the gate length, e.g., the channel area between the source and the drain of a plurality of transistors, operation characteristics of the semiconductor memory device may be degraded.